The present invention relates to a semiconductor storage device and, particularly, resides in a technique that is applicable to a semiconductor device using variable resistance elements.
Patent Document 1 (Japanese Published Unexamined Patent Application No. 2013-200922) describes a verify writing method that, when setting a cell of a Resistance Random Access Memory (ReRAM) in a low resistance state, if the resistance value of the cell has not reached a desired value after the execution of applying a writing pulse and verify reading, repeats a series of processing operations as follows: applying a pulse of opposite polarity→applying a rewriting pulse→verify reading. Patent Document 2 (Japanese Published Unexamined Patent Application No. Hei 06(1994)-60674) and Patent Document 3 (Japanese Published Unexamined Patent Application No. 2005-44454 respectively describe verify writing methods that execute verify writing, while increasing the time during which a writing pulse of the same polarity is applied.